Example embodiments disclosed herein relate to semiconductor memory devices. More particularly, example embodiments disclosed herein relate to a semiconductor memory device that may be capable of improving access performance, and an access method thereof.
Semiconductor memory devices are generally classified into volatile and nonvolatile types. Volatile semiconductor memory devices may operate fast in reading and writing data, but may have a disadvantage of losing data when a power supply is interrupted. The volatile semiconductor memory devices may be divided into dynamic random access memories (hereinafter, referred to as ‘DRAMs’) and static random access memories (hereinafter, referred to as ‘SRAMs’). DRAMs may conduct refresh operations for retaining data stored therein. SRAMs may be able to retain their data even without refresh operations during power supply.
Recently, semiconductor memory devices employed in electronic systems are evolving in operation rate. A synchronous DRAM (hereinafter, referred to as ‘SDRAM’) may be an example of a typical memory device operating in high frequency of hundreds megahertz (Hz) in sync with an external system clock. In an SDRAM, operations of all commands relevant to reading/writing functions may be designed to be active in sync with an external system clock signal.
SDRAMs may be classified into single data-rate types (hereinafter, referred to as ‘SDR-SDRAM’) and double data-rate SDRAMs (hereinafter, referred to as ‘DDR-SDRAM’). DDR-SDRAMs may be twice as wide as SDR-SDRAMs in data transmission bandwidth. In recent years, new-generation normal DRAMs with faster DDR2 and DDR3 modes have been developed and used.
A generic DRAM may be composed of plural banks. Each bank may include pluralities of memory cells arranged on intersections of rows and columns. Generally, an access operation of DRAM may be carried out in a unit of a group of banks including two or more banks. Bank groups may operate independently as a unit DRAM and may accomplish a high-frequency operation. The access operation of the bank group may be conducted with tCCD (a delay time after applying a column address). For instance, if tCCD is set to two clocks (2tCK), a command for accessing a bank group may be transferred to the DRAM and after 2tCK, a command for accessing the next bank group may be transferred to the DRAM. The command may be input in 2 clock periods. After transferring the command for accessing the bank group, the access operation may be carried out to a selected bank and an input/output data signal (DQ) may be enabled with a pulse of 2 clock pulses. After accessing the selected bank group, the access operation may be carried out on the same bank group or another bank group.
As is mentioned above, DRAMs have become faster in operation in recent years. Thus, DRAMs may be operating in high frequency. Since a clock width may become narrower as an operation frequency increases, tCCD may be shortened. A shorter tCCD may make a pulse width of the input/output data (DQ) narrower. If the same bank group is continuously accessed under this condition, there may be a problem of insufficient margin on the input/output data (DQ) due to jitters and noises.
In order to resolve this problem, tCCD may be fixed to a larger value for a sufficient margin. For example, a tCCD of 2 clock pulses (2tCK) may be modified to correspond with 4 clock pulses (4tCK). But if tCCD is set on 4 clock pulses (4tCK), it may lengthen a delay time for accessing a bank group. For example, if there is an input of commands in the period of 2 clock pulses, it may not be permissible to receive 3 commands during 4 clock pulses. Otherwise, if commands are input in the period of 4 clock pulses, it may not be permissible to receive 2 commands during 4 clock pulses. Moreover, as the DRAM is set to process commands input in the period of 4 clock pulses if tCCD is fixed to 4 clock pulses (4tCK), the DRAM may be unable to process commands input in the period of 2 or 3 clock pulses. As a result, the semiconductor memory device may be degraded in access performance when tCCD is fixed to a large value in a high frequency band.